In many memory controllers, particularly dynamic random access memory (DRAM), or video random access memory controllers (VRAM) the address that is asserted from a bus or a CPU must be time multiplexed as a row and column address to be sent to memory. In many cases the address must also be translated. Therefore the memory accesses must be performed in a minimum amount of time. This is important because accessing a memory requires a certain amount of power and power consumption is critical in many computer applications.
In a first prior art implementation, the address translator and the multiplexer path are always enabled. In this embodiment, a valid address begins to propagate to the memory immediately. The advantage of this implementation is that the address begins to propagate through the controller to the memory as soon as the address is valid. The primary disadvantage with this method is that when there are address transitions during unrelated activity on the bus, power is consumed in the input buffer, address translator mux, output buffers and the memory. As has been above mentioned, excessive power consumption is problematic in a portable or laptop computer environment.
A second prior art memory controller implementation disables the input buffer between memory cycles to eliminate the extra power consumption. In many instances a bus will assert a valid address before there is indication that a cycle is starting or that the access will involve the memory controller. Therefore, the memory controller can then detect from the most significant address bits whether it should respond to the access. However, this implementation has the disadvantage that the input buffers are disabled for some period of time after a valid address is available thereby delaying the point in time where the translated address arrives at the memory. Accordingly, the length of the memory access is increased thereby reducing the memory bandwidth.
The present invention overcomes the above-identified problems to produce a memory controller that does not significantly decrease the memory bandwidth and at the same time does not have the power consumption problems unknown with the previously known systems.